1) Field of the Invention
This invention relates generally to devices and methods for the fabrication of semiconductor devices and more particularly to the fabrication of Field Effect Transistors (FETs) having embedded Source/Drain regions and FETs having raised S/D regions.
2) Description of the Prior Art
It is now well-established that raised source/drain (S/D) structures and embedded SiGe (eSiGe) are useful techniques to enhance device performance. However, both techniques involve complicated processes compared to a normal CMOS process flow. Especially for eSiGe, besides the additional process needed for Si recess and epitaxial growth in the PFET S/D region, the eSiGe scheme needs additional process to protect the poly-Si gate as well. It is also extremely difficult to integrate eSiGe in the PFET while having raised S/D structures in the NFET.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. 20050035409A1: Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit—Semiconductor chip for use in semiconductor integrated circuit, comprises semiconductor substrate having first and second active regions, resistor formed in first active region, and strained channel transistor formed in second active region. Inventor: Ko, Chih-Hsin; Kaohsiung, Taiwan
U.S. 20050079692A1: Methods to fabricate MOSFET devices using selective deposition process—Fabrication of silicon-based device on substrate surface involves depositing first and second silicon-containing layers by exposing to specified first and second process gases, respectively Inventor: Samoilov, Arkadii V.; Sunn
U.S. Pat. No. 6,881,635: Strained silicon NMOS devices with embedded source/drain—Formation of n-type field effect transistor involves removing silicon germanide material outside transistor body and below strained silicon layer and replacing the removed material with epitaxial silicon. Inventor: Chidambarrao, Dureseti
U.S. Pat. No. 6,861,318: Semiconductor transistor having a stressed channel—Semiconductor transistor for integrated circuits, comprises source and drain formed in source and drain recesses, respectively, source and/or drain being made of film material, which is formed to have second lattice having second spacing Inventor: Murthy, Anand; The patent shows a process for recessed S/D SiGe regions.
U.S. Pat. No. 6,531,347: Method of making recessed source drains to reduce fringing capacitance—Manufacture of semiconductor device involves forming source and drain regions that are recessed at prescribed depth below semiconductor substrate surface Inventor: Huster, Carl
U.S. Pat. No. 6,849,883: Strained SOI MOSFET device and method of fabricating same—MOSFET device as e.g. large-scale integration circuit comprises first MOSFET with silicon layer in first region serving as strained silicon channel and second MOSFET with silicon epitaxial layer serving as silicon channel—Inventor: Okihara, Masao; Tokyo, Japan
Gene Fitzgerald, “A quick primer on strained silicon”, URL: http://www.eetimes.com/showArticle.jhtml?articleID=18100036 (Feb. 23, 2004 12:00 PM EST) discusses boron doped SiGe epitaxy processes.